The present inventive concept relates to integrated circuit devices, and in particular, to integrated circuit devices including conductive vias.
As semiconductor devices have become more highly integrated and require increasingly higher capacities, three-dimensional (3D) packaging techniques (in which various individual chips are stacked) have been developed. Specifically, packaging techniques in which a via hole penetrating a substrate is formed and an electrode is formed in the via hole (also referred to as through silicon via contact techniques) may be used to augment and/or replace wire bonding techniques. However, as several thousand or more through silicon via contacts may be formed per chip, leakage current may occur due to the through silicon via contacts.